Generally, for integrated circuits in which arithmetic processing or the like is performed in accordance with an operation clock, there is a need for providing large design margins in order to ensure normal operations at all times against variations in manufacturing processes or such variations as power supply variations and temperature changes. That is, in order that the processing time falls within one cycle time of the clock even if the circuit delay is increased by various types of changes or the like so that the processing time is increased, design margin are provided by constructing circuits in parallel fashion to suppress the processing time, or by applying a power voltage higher than that at which the integrated circuit operates normally so that the circuit delay is decreased, or by other means. These large design margins cause obstruction to downsizing or power consumption reduction of integrated circuits.
Thus, there has been proposed a technique for detecting the operating state of an integrated circuit and controlling the power voltage so as to allow a minimum power voltage required for the operation of the integrated circuit can be supplied. The concept of this technique is disclosed in Japanese unexamined patent application No. H08-136621. This technique is to implement an adjustment so that the power voltage becomes as small as possible within such a range that the processing time falls just within the one cycle time of the clock even if the processing time has changed due to variations in manufacturing processes or such variations as power supply variations and temperature changes. That is, if the processing time is increased toward excess over the one-cycle time of the clock, the power voltage is increased so as to suppress the processing time. If the processing time is decreased so that there is a margin for the cycle time of the clock, then the power voltage is lowered. As a result of this, even if the circuit delay is increased, causing the processing time to be increased, due to various types of variations, it is no longer necessary to suppress the arithmetic processing time by making up a parallel construction of circuits, or by applying a power voltage larger than the power voltage at which the integrated circuit normally operates.
The adjustment of the power voltage is implemented in the semiconductor integrated circuit device shown in FIG. 3 as follows.
The semiconductor integrated circuit device, as shown in FIG. 3, includes a power voltage generation circuit 31 for generating a power voltage, a power voltage evaluation circuit 32 for receiving a generated power voltage as an input and producing a control signal as an output, and an internal circuit 33 for receiving a generated power voltage as an input and performing specified processing.
The control signal outputted from the power voltage evaluation circuit 32 adjusts the power voltage so that the power voltage becomes as low as possible within a range over which the internal circuit 33 normally operates. More specifically, an inverter train that causes a signal delay equivalent to a critical path (signal path having the longest number of logic gate stages) in the internal circuit 33 is provided in the power voltage evaluation circuit 32 as a delay evaluation circuit, and a control signal is outputted based on a delay amount detected by the delay evaluation circuit. For example, if the delay amount is smaller than a lower-limit set value, which implies a higher operating speed of the internal circuit, then a control signal that causes the power voltage to be decreased is outputted. On the other hand, if the delay amount is larger than an upper-limit set value, which implies a lower operating speed of the internal circuit, then a control signal that causes the power voltage to increase is outputted. Also, if the delay amount is not less than the lower-limit set value and not more than the upper-limit set value, which implies a proper operating speed of the internal circuit, then a control signal that makes the power voltage held is outputted. In this way, a operating state of the delay evaluation circuit is detected, and the power voltage generated from the power voltage generation circuit 31 is controlled so as to give the internal circuit 33 a power voltage that is a minimum required for its operation.
In another case, there has been proposed a technique for extremely lowering the power voltage in order to reduce the power consumption of a semiconductor integrated circuit device to a large extent. In a semiconductor integrated circuit device, since power consumption of the integrated circuit due to switching is proportional to the square of the power voltage, it is effective to lower the power voltage in terms of power consumption reduction, but there is a problem that lowering the power voltage alone would cause the ON-state current of a MOS transistor to decrease, inhibiting the high-speed operation. To avoid this problem, the absolute value of the threshold voltage of the MOS transistor needs to be decreased in accordance with the decrease of the power voltage. However, decreasing the absolute value of the threshold voltage would give rise to another problem that the OFF-state current by a subthreshold current of the MOS transistor to increase.
As a MOS transistor circuit for relieving such an OFF-state current increase issue, there has been proposed a method in which a semiconductor substrate (or well) with a MOS transistor formed thereon is connected to the gate terminal and the threshold voltage of the MOS transistor is controlled by the voltage of the gate terminal, as disclosed in JP 08-12917 A. That is, as shown in FIG. 4, in the state that the semiconductor substrate (or well) with an N-type MOS transistor 41 formed thereon and the gate terminal of the N-type MOS transistor 41 are connected to each other, when a voltage that causes the N-type MOS transistor 41 to turn on (i.e., a positive voltage relative to a source voltage Vs) is applied to the gate terminal as a gate voltage Vg, the same voltage is applied also to the semiconductor substrate (or well) and therefore the threshold voltage decreases in absolute value equivalently, causing the ON-state current to increase. On the other hand, when a voltage that causes the N-type MOS transistor 41 to turn off (i.e., an equal or negative voltage relative to the source voltage Vs) is applied to the gate terminal as a gate voltage Vg, the same voltage is applied also to the semiconductor substrate (or well) and therefore the threshold voltage increases in absolute value equivalently, causing the OFF-state current to decrease.
For example, in the above MOS transistor circuit, the relationship between gate voltage Vgs and drain current Ids of the N-type MOS transistor 41 can be set as shown in FIG. 5, where the ON-state current can be made as large as 10−4 A/μm, comparable to that of common MOS transistors of low threshold voltage, while the OFF-state current can be made as small as 10−10 A/μm, comparable to that of common MOS transistors of high threshold voltage.
Although an N-type MOS transistor has been shown in FIG. 4, the case is the same also with a P-type MOS transistor. That is, when a voltage that causes a P-type MOS transistor to turn on (i.e., a negative voltage relative to a source voltage Vs) is applied to the gate terminal as a gate voltage Vg, the same voltage is applied also to the semiconductor substrate (or well) with the P-type MOS transistor formed thereon and therefore the threshold voltage decreases in absolute value equivalently, causing the ON-state current to increase. On the other hand, when a voltage that causes the P-type MOS transistor to turn off (i.e., an equal or positive voltage relative to the source voltage Vs) is applied to the gate terminal as a gate voltage Vg, the same voltage is applied also to the semiconductor substrate (or well) and therefore the threshold voltage increases in absolute value equivalently, causing the OFF-state current to decrease.
FIG. 6 shows a CMOS (Complementary Metal-Oxide Semiconductor) inverter circuit formed by using the MOS transistors connecting such a semiconductor substrate (or well) to the gate terminal.
Hereinbelow, for simplicity of explanation, it is assumed that both a P-type MOS transistor 61 and an N-type MOS transistor 62 have characteristics shown in FIG. 5. A semiconductor substrate (or well) with the P-type MOS transistor 61 and the N-type MOS transistor 62 formed thereon is connected a gate terminal of the P-type MOS transistor 61 and the N-type MOS transistor 62 (i.e., to an input terminal 63 of a CMOS inverter circuit, and voltages Vsubp, Vsubn of the semiconductor substrate (or well) are equal to a voltage Vin of the input terminal 63.
Accordingly, in the case where the voltage Vin of the input terminal 63 is equal to a ground voltage Gnd, a turn-ON voltage is applied to the gate terminal of the P-type MOS transistor 61, so that the threshold voltage decreases in absolute value equivalently, causing the ON-state current to increase to as large as 10−4 A/μm (current value for each 1 μm of channel width). Simultaneously with this, a turn-OFF voltage is applied to the gate terminal of the N-type MOS transistor 62, so that the threshold voltage increases in absolute value equivalently, causing the OFF-state current to decrease to as small as 10−10 A/μm. On the other hand, in the case where the voltage Vin of the input terminal 63 is equal to the power voltage Vdd, a turn-OFF voltage is applied to the P-type MOS transistor 61, so that the threshold voltage increases in absolute value equivalently, causing the OFF-state current to decrease to as small as 10−10 A/μm. Simultaneously with this, a turn-ON voltage is applied to the N-type MOS transistor 62, so that the threshold voltage decreases in absolute value equivalently, causing the ON-state current to increase to as large as 10−4 A/μm.
As shown above, the ON-state current for the P-type MOS transistor 61 and the N-type MOS transistor 62 to be turned ON becomes 10−4 A/μm, causing the drive current for the CMOS inverter circuit to be as large as 10−4 A/μm, while the OFF-state current for the P-type MOS transistor 61 and the N-type MOS transistor 62 to be turned OFF becomes 10−10 A/μm so that a leak current flowing from the power voltage terminal to the ground voltage terminal becomes as small as 10−10 A/μm.
From now onward, as the further micro-fining of integrated circuits as well as the reduction of power voltage advance on and on, the effects of variations in manufacturing processes or such variations as power supply variations and temperature changes on the processing speed would become larger, and moreover in OFF-state current increase issue due to decrease of threshold voltage would matter. Therefore, a power voltage control technique such as shown in FIG. 3 as well as a MOS transistor circuit in which a semiconductor substrate (or well) such as shown in FIG. 6 is connected to the gate terminal are effective.
However, when the power voltage control technique of the semiconductor integrated circuit device shown in FIG. 3 and the MOS transistor circuit shown in FIG. 6 are combined together, there are issues as follows.
With the use of the power voltage control technique, there is a case where the power voltage increases beyond the built-in potential (diffusion potential) in response to variations in manufacturing processes or such variations as power supply variations and temperature changes. Since the semiconductor substrate (or well) on which MOS transistors composing the MOS transistor circuit are formed are connected to the gate terminal, the power voltage that has become over the built-in potential would cause the a voltage over the built-in potential to be applied to between the semiconductor substrate (or well) and the source terminal. As a result, a current would flow between the semiconductor substrate (or well) and the source terminal (i.e., between the gate terminal and the source terminal), so that the gate current would increase considerably, posing problems such as unstable operation of the MOS transistor circuit or increased current consumption thereof.